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d a t a sh eet product speci?cation file under integrated circuits, ic20 1996 mar 22 integrated circuits 83c145; 83c845 83c055; 87c055 microcontrollers for tv and video (mtv)
1996 mar 22 2 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 contents 1 features 2 description 3 applications 4 ordering information 5 block diagram 5.1 part options 6 pinning information 6.1 pinning 6.2 pin description 7 description of standard functions 8 input/output (i/o) 9 description of derivative functions 9.1 general description 10 6-bit pwm dacs 10.1 pwm dac operation 10.2 special function register pwmn (n = 0 to 7) 11 14-bit pwm dac (tdac) 11.1 14-bit counter 11.2 14-bit dac operation 11.3 special function register tdacl 11.4 special function register tdach 12 software analog-to-digital facility 12.1 special function register sad 12.2 software adc operation 13 on screen display (osd) 13.1 osd features 13.2 general description of the osd module 13.3 osd logic 13.4 character generator rom 13.5 display ram organization 13.6 osd special function registers 13.7 osd control register oscon 13.8 osd control register osmod 13.9 osd control register osorg 14 programming considerations 14.1 eprom characteristics 14.2 programming operation 14.3 erasure characteristics 14.4 reading signature bytes 14.5 eprom programming and verification 15 programming the osd eprom 15.1 overview 15.2 character description and programming 15.3 osd eprom bit map 16 register map 17 limiting values 18 handling 19 dc characteristics 20 ac characteristics 21 package outlines 22 soldering 22.1 introduction 22.2 soldering by dip or wave 22.3 repairing soldered joints 23 definitions 24 life support applications
1996 mar 22 3 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 1 features masked rom sizes: C 8 kbytes (83c845) C 12 kbytes (83c145) C 16 kbytes (83c055) C 16 kbytes otp (87c055) ram: 256 bytes on screen display (osd) controller three digital video outputs multiplexer/mixer and background intensity controls flexible formatting with osd new line option 128 10 bits display ram designed for reduced radio frequency interference (rfi) character generator rom: C character format 18 lines 14 dots C 60 visible characters C 4 special characters eight text shadowing modes text colour selectable per character background colour selectable per word background colour versus video selectable per character eight 6-bit pulse width modulators (pwm) for analog voltage integration one 14-bit pwm for high-precision voltage integration digital-to-analog converter and comparator with 3 inputs multiplexer nine dedicated i/os plus 28 port bits (15 port bits with alternative uses) 4 high current open-drain port outputs 12 high voltage (+12 v) open-drain outputs programmable video input and output polarities 80c51 instruction set no external memory capability plastic shrink dual in-line package (0.07 inch centre pins) high-speed cmos technology power supply: 5 v 10%. 2 description the 83c055, microcontroller for television and video (mtv) applications, is a derivative of philips industry standard 80c51 microcontroller. the 83c055 is intended for use as the central control mechanism in a television receiver or tuner. 3 applications providing tuner functions and an osd facility, it represents a next generation replacement for the currently available parts. 4 ordering information type number package temp. range ( c) freq. (mhz) name description version p83c055bbp sdip42 plastic shrink dual in-line package; 42 leads (600 mil) sot270-1 0 to +70 3.5 to 12 p87c055bbp P83C145BBP p83c845bbp
1996 mar 22 4 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 5 block diagram 5.1 part options table 1 differences between the types memory types 83c845 83c145 83c055 87c055 rom 8 kbytes 12 kbytes 16 kbytes - eprom (otp) --- 16 kbytes fig.1 block diagram. handbook, full pagewidth 80c51 core excluding rom / ram 8-bit internal bus 8-bit timer / event counter cpu rom (1) 8 x 6-bit pwm software control adc v ss p3 p2 p1 pwm0 to pwm7 vid2 vid1 bf vid0 vctrl vclk1 vclk2 vsync hsync v dd xtal1 (in) xtal2 (out) 14-bit pwm ram 256 bytes tdac adi2 to adi0 mbe766 t0 int0 int1 parallel i / o ports 88 8 4 p0 8 3 display ram 128 10 character generator rom 60 18 14 rst osd block (1) rom sizes: see table 1.
1996 mar 22 5 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 6 pinning information 6.1 pinning fig.2 pin configuration (sot270-1). handbook, halfpage handbook, halfpage 83c145 83c845 83c055 87c055 mbe765 1 2 42 41 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 v dd p3.7 p3.6 p3.5 p3.4 p3.3/int0 p3.2/t0 p3.1/int1 p3.0 rst xtal2 xtal1 bf vclk2 vclk1 vsync hsync vctrl vid2 vid1 vid0 v pp /tdac/p0.0 prog/pwm1/p0.1 asel/pwm2/p0.2 pwm3/p0.3 pwm4/p0.4 pwm5/p0.5 pwm6/p0.6 pwm7/p0.7 adi0/p1.0 adi1/p1.1 adi2/p1.2 pwm0/p1.3 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 v ss
1996 mar 22 6 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 6.2 pin description table 2 pin description sdip42 (sot270-1) symbol pin description port 0 (notes 1 , 2 and 4) p0.0/tdac/v pp 1 p0.0 : open-drain bidirectional port line; tdac : output for the 14-bit high-precision pwm; v pp : 12 v programming supply voltage during eprom programming. p0.1/pwm1/prog 2 p0.1 : open-drain bidirectional port line; pwm1 : output for the 6-bit lower-precision pwm; prog : input for eprom programming pulses. p0.2/pwm2/asel 3 p0.2 : open-drain bidirectional port line; pwm2 : output for the 6-bit lower-precision pwm; asel : input indicating the eprom address bits that are applied to port 2. p0.3/pwm3 to p0.7/pwm7 4to8 p0.3 to p0.7 : 5 open-drain bidirectional port lines; pwm3 to pwm7 : 5 outputs for the 6-bit lower-precision pwm. port 1 (notes 1 , 2 and 5) p1.0/adi0 to p1.2/adi2 9to11 p1.0 to p1.2: 3 open-drain bidirectional port lines; adi0 to adi2 : inputs for the software analog-to-digital facility. p1.3/pwm0 12 p1.3 : open-drain bidirectional port line; pwm0 : output for the 6-bit lower-precision pwm. pwm0 can be externally pulled up as high as +12 v 5% port 2 p2.7 to p2.0 13 to 20 port 2 : 8-bit open-drain bidirectional port; p2.3 to p2.0 have high current capability (10 ma at 0.5 v) for driving leds. port 2 pins that have logic 1s written to them ?oat, and in that state can be used as high-impedance inputs. any of the port 2 pins are driven low if the port register bit is written as a logic 0. the state of the pin can always be read from the port register by the program. port 3 (note 1 and 3) p3.0 34 p3.0 : open-drain bidirectional port line. p3.1/int1 35 p3.1 : open-drain bidirectional port line; int1 : external interrupt 1. p3.2/t0 36 p3.2 : open-drain bidirectional port line; t0 : timer 0 external input. p3.3/int0 37 p3.3 : open-drain bidirectional port line; int0 : external interrupt 0. p3.4 to p3.7 38 to 41 p3.4 to p3.7 : 4 open-drain bidirectional port lines. general v ss 21 ground : 0 v reference. vid2 to vid0 22 to 24 digital video bus : three totem-pole outputs comprising digital rgb (or other colour encoding) from the osd facility. the polarity of these outputs is controlled by a programmable register bit (register oscon; bit po). vctrl 25 video control : a totem-pole output indicating whether the osd facility is currently presenting active video on the vid2 to vid0 outputs. signal is used to control an external multiplexer (mixer) between normal video and the video derived from vid2 to vid0. the polarity of this output is controlled by a programmable register bit (register oscon; bit pc).
1996 mar 22 7 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 notes 1. port 0, port 1 , and port 3 pins that have logic 1s written to them ?oat, and in that state can be used as high-impedance inputs. 2. the state of the pin can always be read from the port register by the program. 3. p3.0, p3.4, and p3.7 can be externally pulled up as high as +12 v 5%; while p3.5 and p3.6 have 10 ma drive capability. 4. for each pwm block, a register bit (register pwmn; bit pwne; n = 0 to 7) controls whether the corresponding pin is controlled by the block or by port 0; port 0 controls the pin immediately after a reset. regardless of how each pin is controlled, it can be externally pulled up as high as +12 v 5%. 5. any of the port 1 pins are driven low if the corresponding port register bit is written as a logic 0, or for p1.3 only, if the tdac module presents a logic 0. hsync 26 horizontal sync : a dedicated input for a ttl-level version of the horizontal sync pulse. the polarity of this pulse is programmable; its trailing edge is used by the osd facility as the reference for horizontal positioning. vsync 27 vertical sync : a dedicated input for a ttl-level version of the vertical sync pulse. the polarity of this pulse is programmable, and either edge can serve as the reference for vertical timing. vclk1 28 vclk1: video clock 1 ; input for the horizontal timing reference for the osd facility. vclk2: video clock 2 ; output from the on-chip video oscillator. vclk1 and vclk2 are intended to be used with an external lc circuit to provide an on-chip oscillator. the period of the video clock is determined such that the width of a pixel in the osd is equal to the inter-line separation of the raster. vclk2 29 bf 30 background/foreground : a totem-pole output which, when vctrl is active, indicates whether the current video data represents a foreground (low) or background (high) dot in a character. this signal can be used to reduce the intensity of the background colour and thus emphasize the text. xtal1 31 xtal1 : input to the inverting (oscillator) ampli?er and clock generator circuit that provides the timing reference for all 83c055 logic other than the osd facility. xtal2 : oscillator output terminal for system clock. xtal1 and xtal2 can be used with a quartz crystal or ceramic resonator to provide an on-chip oscillator. alternatively, xtal1 can be connected to an external clock, and xtal2 left unconnected. xtal2 32 rst 33 reset : if this pin is high for two machine cycles (24 oscillator periods) while the oscillator is running, the mtv is reset. this pin is also used as a serial input to enter a test or eprom programming mode, as on the 87c751. v dd 42 power supply : for normal and power-down operation. symbol pin description
1996 mar 22 8 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 7 description of standard functions for a description of the standard functions please refer to the data handbook ic20; section 2: 80c51 technical description . 8 input/output (i/o) the i/o structure of the 83c055 is similar to the standard i/o structure in the 80c51, except for the points described in table 5. 9 description of derivative functions 9.1 general description although the 83c055 is specifically referred to throughout this data sheet, the information applies to all the devices. the differences to 80c51 features and the derivative functions are described in the following sections and chapters. figure 1 shows the block diagram of the 83c055. 9.1.1 n ot implemented functions standard functions to the 80c51 that are not implemented in the 83c055: as data and program memory are not externally expandable on the 83c055, the ale, ea, and psen signals are not implemented. idle mode. power-down mode. 9.1.2 i nterrupt facilities differences the interrupt facilities of the 83c055 differ from those of the 80c51 as follows: the ip register is not used, and the ie register (address a8h) is similar to that on the 80c51;see table 36. the vsync input used by the osd facility can generate an interrupt. the active polarity of the pulse is programmable (see section 13.7); interrupt occurs at the leading edge of the pulse. since there is no serial port, there are no interrupts nor control bits relating to this interrupt. the interrupts and their vector addresses are shown in table 3. external interrupt 1 is modified so that an interrupt is generated when the input switches are in either direction (on the 80c51, there is a programmable choice between interrupt on a negative edge or a low level on int1). this facility allows for software pulse-width measurement handling of a remote control. table 3 program memory address 9.1.3 pcon r egister difference the pcon register format is shown in table 4. bits gf1 and gf0 are general purpose flag bits. table 4 pcon register format (address 87h) event program memory address reset 000h external int0 003h timer 0 00bh external int1 013h timer 1 01bh vsync start 023h 76543210 ---- gf1 gf0 -- 9.1.4 i/o ports differences table 5 i/o ports differences i/o standard 80c51 83c055 port 0 external memory expansion 8-bit open-drain bidirectional port; and includes: alternative use for pwm outputs port 1 8-bit general purpose quasi-bidirectional 4-bit open-drain port, and includes alternative uses for analog inputs and a pwm output port 2 quasi-bidirectional and can be used for external memory expansion open-drain and general purpose port 3 quasi-bidirectional; all eight bits have alternate uses 3 port bits have some of the same alternative uses as on the 80c51 but not necessarily on the same pins; 5 pins are open-drain and general purpose
1996 mar 22 9 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 10 6-bit pwm dacs figure 3 shows the 6-bit pwm dac logic circuit, consisting of 8 pwmn modules. the basic mcu clock is divided by 4 to get a waveform that clocks a 14-bit counter which is common to all the pwms (including the 14-bit pwm). this divided clock is hereafter called the pwm clock. as illustrated in fig.3, the lower-precision (6-bit) pwms use the least significant part of the 14-bit counter. figure 4 shows the circuit diagram of a 6-bit pwm module. each pwm module has a special function register pwmn; n = 0 to 7. the register format is shown in table 6. 10.1 pwm dac operation value field pvn5 to pvn0 of each pwmn register (n = 0 to 7) is compared to the 6 lsbs of the common counter (14-bit counter). when the value matches, the output flip-flop is cleared, so that the output pin is driven low. when the value rolls over to zero, the output flip-flop is set, so that the output pin is released. thus the output waveform has a fixed period of 64 pwm clock cycles; its duty cycle is determined by contents of pwmn.5 to pwmn.0 (pvn5 to pvn0). three of the nine total pwm modules (8 pwmn and the 14-bit pwm dac) operate as previously described; for three others, both the rising and falling edges of the output are delayed by one pwm clock; for the remaining three, both edges are delayed by two pwm clocks. this feature reduces the radio-frequency emission that would otherwise occur when the counter rolled over to zero and all nine open-drain outputs were released. 10.2 special function register pwmn (n = 0 to 7) table 6 special function register pwmn (n = 0 to 7; addresses d4h to dfh) table 7 description of pwmn bits 7 6 5 4 3 2 1 0 pwne - pvn5 pvn4 pvn3 pvn2 pvn1 pvn0 bit symbol description 7 pwne pwm module enable bit. if for a particular pwm block (n) the bit: pwne = 1, then the block is active and controls its assigned port pin. pwne = 0, the corresponding port pin is controlled by the port. 6 - reserved. 5 to 0 pvn5 to pvn0 value field for pwmn register.
1996 mar 22 10 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 handbook, full pagewidth pwm0/p1.3 pwm1/p0.1 pwm7/p0.7 p1.3 p0.1 p0.7 p0.2 to p0.6 pwm2/p0.2 to pwm6/p0.6 1st pwm module (n = 0) 2nd pwm module (n = 1) 8th pwm module (n = 7) 3rd to 7th pwm module (n = 2 to 6) internal bus 14-bit counter 4 14-bit pwm dac block f xtal zero 8 8 8 8 8 6 6 6 6 6 ls 6-bits pwm clock mbe771 - 1 fig.3 6-bit pwm dac logic circuit. fig.4 a 6-bit pwm module. handbook, full pagewidth pwmn i/o pin 6-bit comparator pvn0 pvn1 pvn2 pvn3 pvn4 pvn5 pwne pwm module (n) zero ls 6-bits internal bus pwm clock (1) (2) i/o port 6-bits (pvn0 to pvn5) mbe770 8 (1) this flip-flop occurs in 5 of the 8 pwmn modules. (2) this flip-flop occurs in 3 of the 8 pwmn modules.
1996 mar 22 11 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 11 14-bit pwm dac (tdac) 11.1 14-bit counter the 14-bit counter was already mentioned in section 10. the nature of the counter is such that it can achieve a stable output value through its msb, and the value can propagate through logic like that shown in fig.5. the logic output can be stable within: one period of the pwm clock (e.g. 250 ns) if edge-triggered logic is used to capture the logic output, or one phase of the pwm clock (e.g. 125 ns) if a phase of the pwm clock is used to capture the logic output. the 14-bit (tdac) counter is a ripple counter (cost and die-size reasons). the 14-bit pwm dac is controlled by two special function registers tdacl and tdach. 11.2 14-bit dac operation when software wishes to change the 14-bit value (td0 to td13), it should first write to tdacl and then write to tdach. alternatively, if the required precision of the duty cycle is satisfied by 6 bits or less, software can simply write to tdach (td8 to td13). 11.2.1 l ow precision operation figure 5 shows that this block includes an extra 14-bit latch between tdacl - tdach and the comparator and other logic. the programmed value is clocked into the operative latch when the 7 low-order bits of the counter roll over to zero, provided that the software is not in the midst of loading a new 14-bit value, i.e. it is not between writing tdacl and writing tdach. in a similar fashion to the lower-precision pwms, this facility has an output flip-flop that is set when the lower 7 bits of the counter overflow/wrap. the more significant 7 bits of the operative latchs programmed value are compared for equality against the less significant 7 bits of the counter, and the output ff is cleared when they match. thus this output has a fixed period of 128 pwm clock cycles, and the duty cycle is determined by the programmed value. 11.2.2 h igh precision operation for the higher-precision aspect of this feature, the 7 msbs of the counter are used in a logic block with the 7 lsbs of the programmed value. the 7 th lsb (binary value 64) of the programmed value is anded with the 7 th msb (128) of the counter, the 6 th lsb of the value is anded with the counters 6 th and 7 th msbs being 10, and so on through the lsb of the programmed value being anded with the counters 7 msbs being 100000. then these 7 anded terms are ored. if the result is true (logic 1) at the time the 7 lsbs of the counter match the msbs of the programmed value, the output is forced high for 1 (additional) pwm clock cycle. the result is that, if the value-64 bit of the 14-bit value is programmed to a logic 1, every other cycle of 128 pwm counter clocks has its duty cycle stretched by one counter clock; if the value-32 bit is programmed to logic 1, every 4 th cycle is stretched, and so on through, if the value-1 bit is programmed to logic 1, one cycle out of each 128 is stretched. 11.2.3 14- bit dac output assuming the external integrator can handle all this, the net effect is a pwm dac that has the period of a 7-bit design (which makes the integrator easier and more feasible to design) with the accuracy of a 14-bit one. an obvious prerequisite for such precision is that the load on the voltage must be very light, like a single op-amp or comparator. 11.2.3.1 note the tdac feature differs from the corresponding features of predecessor parts in several ways: 1. the 14-bit value is functionally composed of major and minor portions of 7 bits each. 2. the 14-bit value is programmed as a contiguous multi-register value that can be manipulated straight-forwardly via arithmetic instructions. 3. as discussed for the 6-bit dacs, both of the preceding parts had a feature whereby the pwm output could be inverted, redundantly with complementing the 14-bit value. this feature has been eliminated.
1996 mar 22 12 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 11.3 special function register tdacl table 8 special function register tdacl format (address d2h) table 9 description of tdacl bits 11.4 special function register tdach table 10 special function register tdach format (address d3h) table 11 description of tdach bits 76543210 td7 td0 td1 td2 td3 td4 td5 td6 bit symbol description 7 to 0 td7, td0 to td6 8 lsbs of the 14-bit value. 76543210 tde - td13 td12 td11 td10 td9 td8 bit symbol description 7 tde enable bit. 6 - reserved. 5 to 0 td13 to td8 6 msbs of the 14-bit value.
1996 mar 22 13 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 fig.5 14-bit pwm logic circuit. handbook, full pagewidth tdach tdacl 14-bit latch 14-bit counter 7 msb 7 lsb 7 7 8 8 7 7 7-bit comparator 7 lsb 7 msb 7 7 7 internal bus pwm clock 4 f xtal p0.0 tdac/ p0.0 tdach.7 mbe774 8 8
1996 mar 22 14 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 12 software analog-to-digital facility figure 6 shows the software analog-to-digital facility block diagram. the block includes special function register sad. 12.1 special function register sad table 12 special function register sad format (address d8h) table 13 description of sad bits 76543210 vhi ch1 ch0 st sad3 sad2 sad1 sad0 bit symbol description 7 vhi the comparator output bit; bit addressable. 6 ch1 the channel field controls which pin, if any, is connected to this facility; see table 14. 5 ch0 4 st the st bit should be written as a logic 1 in order to initiate a voltage comparison. 3 to 0 sad3 to sad0 4 lsbs of the sad register. 12.2 software adc operation port pins p1.0/adi0 to p1.2/adi2 can be alternately selected as inputs of a linear voltage comparator. the other input of the comparator is connected to a 4-bit dac. this dac is controlled by bits sad3 to sad0 and produces a reference voltage: nominally 0.15625 to 4.84375 v in increments of 0.3125 v. the output of the comparator (high or low) can be read by the program as the msb of the sad register i.e. bit vhi. after writing st = 1, the program should include intervening instructions totalling at least 6 machine cycles (72 clock periods or 6 m s at 12 mhz), before the instruction that accesses and tests vhi. table 14 pin selection: p1.n/adin note 1. port 1 has open-drain drivers which will not materially affect an analog voltage as long as any and all pins used for software analog-to-digital measurement have corresponding logic 1s in the port register; n = 0, 1, 2. ch1 ch0 p1.n/adin (1) 0 0 none 0 1 p1.0/adi0 1 0 p1.1/adi1 1 1 p1.2/adi2
1996 mar 22 15 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 fig.6 software analog-to-digital facility. handbook, full pagewidth mbe772 p1.0/adi0 p1.1/adi1 p1.2/adi2 analog mux sad.6:5 sad.3:0 4-bit dac i/o port i/o port i/o port internal bus voltage comparator
1996 mar 22 16 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 13 on screen display (osd) figure 7 shows the osd block diagram. it shows the cpu writing into the 128 10 display ram, which is dual-ported to allow the cpu to write into it at any time, including when it is being read out by the osd logic. the 10-bit wide data coming out of the display ram is used to access the appropriate character in the character generator memory (6-bits) and to specify character and display control functions (4-bits). timing for the osd is controlled by the hsync, vsync, and dot clock input vclk1. 13.1 osd features the 83c055 features an advanced osd function with some unique features as described in sections 13.1.1 to 13.1.10. 13.1.1 u ser - definable display format the osd does not restrict the user to a fixed number of lines with a fixed number of characters per line: using a fixed number of lines restricts the generation of displays that can be differentiated from others that use the same chip and places limits on screen content. using a fixed number of characters per line wastes display ram if a line has less than the full number of displayable characters (it has to be padded with non-visible characters). the osd on the 83c055 defines a control character: new line, that has the same function as a carriage return and line feed. when the osd circuitry fetches this character from display ram it stops displaying further characters, waits for the next horizontal scan line, and starts displaying the next character in display ram after the new line character was received. the number of lines is thus up to the user, within the limits of the display and memory, as are the number of characters per line. this allows far better control of the appearance of the osd. 13.1.2 c olours selectable by character characters can be displayed on a background of the base video or a programmable background colour. the background colour is selectable by word and the choice of background (base video/user programmed colour) by character. 13.1.3 d ual -p orted d isplay ram the osd has a true display ram instead of a character line buffer. this display ram is dual-ported to allow updating the display ram at any time instead of having to wait for a vertical retrace. vertical sync (vsync) interrupts are supported if flicker-free updates are required. 13.1.4 p rogrammable character size normal characters are displayed as 18 14 bit maps. in an interlaced display: C 2 fields are displayed so that one actually sees a 36 14 pixel size character. C the part has a double height and width mode which displays 36 28 pixel size bit maps per field. for use in non-interlaced systems, the part has a double height mode so that the displayed characters have the same pixel size (36 14) as on an interlaced display. 13.1.5 c haracter shadowing when characters are displayed overlaid on a background of base video, a black border around the characters makes them highly legible. this feature is called shadowing. the 83c055 has 8 shadowing modes to allow the user to select various partial shadow modes as well as full surround shadow; see fig.8 and table 28. 13.1.6 p rogrammable polarities inputs to and outputs from the osd can be programmed to be recognized as active low or high. in conjunction with the 12 v outputs, this allows direct interfacing to most video signal processing circuits. 13.1.7 c haracter g enerator memory in eprom on the 87c055, the character generator memory is in eprom. this feature allows quick and inexpensive font development and refinement against the alternative of creating a masked rom version to see how the final fonts will appear. 13.1.8 hsync locked dot clock oscillator the 83c055 is designed to use an lc oscillator circuit that is started at the trailing edge of hsync and stopped at its leading edge. in practice, this gives a highly consistent delay from hsync to oscillator start and is stable from scan line to scan line so that no left margin effects are seen.
1996 mar 22 17 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 13.1.9 s hort r ows this mode only displays 4 horizontal lines and is used for generating underlines. 13.1.10 p rogrammable horizontal and vertical positions bit pairs hs4 to hs0 and vs2 to vs0 in register osorg (table 30) define the starting point of the display. 13.2 general description of the osd module this block is the largest of the additions that are specific to this product. its basic function is to superimpose text on the television video image, to indicate various parameters and settings of the receiver or tuner. external circuitry handles the mixing (multiplexing) of the text and the tv video. the osd block has 4 input pins: two for a video clock: vclk1 and vclk2 horizontal sync signal: hsync vertical sync signal: vsync. the block has 4 outputs: 3 colour video signals a control signal. since this block is the major feature of the part, its main inputs and outputs are dedicated pins, without alternate port bits. the osd of the 83c055 differs from that in preceding devices in one major way: it does not fix the number and size of displayed rows of text. several predecessor parts allowed two displayed rows of 16 characters each. the 83c055 simply has 128 locations of display ram, each of which can contain: a displayed character, or a new line character that indicates the end of a row. a variant of the new line character is used to indicate the end of displayed data. a number of changes in the osd architecture have reduced the number of other special function registers involved in the feature, below the number needed with predecessor devices: 1. the elimination of certain options such as 4, 6, or 8 character sizes and alternate use of two of the video outputs. 2. the moving of certain other options from central registers to display ram, such as foreground colour codes (fcolor) and background (b) selection. figure 7 shows the 3 major elements of the osd facility: osd logic display ram character generator rom. 13.3 osd logic for a standard ntsc tv signal with an hsync frequency of 15.750 khz and a vsync frequency of nominally 60 hz, there are roughly 50 m s of active horizontal scan line available. a typical pixel clock frequency is 8 mhz, and therefore roughly 400 pixels of resolution can be obtained. at 14 dots per character, this means 28 character per horizontal scan line. if the 12 dot per character display mode is used, that means 33 character per horizontal scan line. allowing for edge effects, 26 characters (14 across) or 31 characters (12 across) can be displayed. note that vga rates and higher can be used. the minimum character dot size will be a function of the vga frequency used. for a 640 480 display, running at 33 khz, the equivalent 83c055 pixel resolution is about 160 across (because of the 8 mhz clock and allowing for overscan). this means that status and diagnostic information can be displayed on video monitors. 13.3.1 on - chip video oscillator the video clock pins (vclk1 and vclk2) are used to connect a lc circuit to an on-chip video oscillator that is independent of the normal mcu clock. the l and c values are chosen so that a video pulse, of a duration equal to the vclk period, will produce a more-or-less square dot on the screen, that is, a dot having a width approximately equal to the vertical distance between consecutive scan lines. the video oscillator is stopped (with vclk2 = low) while: hsync (horizontal sync) is maintained, and is released to operate at the trailing edge of hsync. this technique helps provide uniform horizontal positioning of characters/dots from one scan line to the next.
1996 mar 22 18 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 13.4 character generator rom character generator rom. containing 60 displayable bit maps, i.e. 64 minus 4, comprising: one for each of new line: new line, and three space characters: C space C bspace C splitbspace. each bit map includes 18 scan lines by 14 dots. the character generator rom is maskable or programmable along with the program rom to allow for various character sets and languages. 13.5 display ram organization each display ram location includes: 6 data bits, and 4 attribute bits. the 6 data bits from display ram, along with a line-within-row count, act as addresses into the character generator rom. except in special test modes that are beyond the scope of this data sheet, display ram cannot be read by the mcu program. fig.7 osd block diagram. d book, full pagewidth mbg323 character generator address logic 6 character generator 60 18 14 rgb digital video out osd ram 128 10 attribute control 6 4 7 osd logic hsync vsync vclk2 vclk1 7 internal bus vctrl vid2 vid0 vid1
1996 mar 22 19 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 13.6 osd special function registers the programming interface to display ram is provided by three special function registers as shown in tables 15, 17 and 20. writing osat simply latches the attribute bits into a register, while writing osdt causes the data bus information, plus the contents of the osat register, to be written into display ram. thus, for a given display ram location, osat should be written before osdt. if successive characters are to be written into display ram with the same attributes, osat need not be rewritten for each character, only prior to writing osdt for the first character with those particular attributes. the osat attribute bits associated with the bspace, splitbspace and new line characters (see table 19) are interpreted differently from those that accompany other data characters. with bspace and splitbspace, b is interpreted as described above, but the 3 colour bits specify the background colour (bcolor) for subsequent characters. for bspace, a change in b and bcolor becomes effective at the left edge of the characters bit map. 13.6.1 s pecial f unction r egister osad table 15 special function register osad (on screen address; address 9ah) table 16 description of osad bits 13.6.2 s pecial f unction r egister osdt writing osdt causes the data bus information, plus the contents of the osat register, to be written into display ram. table 17 special function register osdt (on screen data; address 99h) table 18 description of osdt bits 76543210 - osad6 osad5 osad4 osad3 osad2 osad1 osad0 bit symbol description 7 - reserved. 6 to 0 osad6 to osad0 these 7-bits hold the display ram address into which data will be loaded. osad is automatically incremented by one each time osdt and display ram are written to. 76543210 -- osdt5 osdt4 osdt3 osdt2 osdt1 osdt0 bit symbol description 7to6 - reserved. 5 to 0 osdt5 to osdt0 character data; see table 19. in reality, there is a potential con?ict between the timing of a write to osdt and an access to display ram by the osd logic for data display. this is resolved by the use of a true dual-ported ram for display memory.
1996 mar 22 20 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 table 19 special characters related to osdt register 13.6.3 s pecial function register osat table 20 special function register osat ( on screen attributes; address 98h) table 21 description of osat bits special character osdt5 osdt4 osdt3 osdt2 osdt1 osdt0 new line 1 1 1 1 0 1 space (normal) 1 1 1 1 0 0 bspace 1 1 1 1 1 0 splitbspace 1 1 1 1 1 1 with osdt = 76543210 new line --- e - sr d sh bspace --- b - bc2 bc1 bc0 splitbspace --- b - bc2 bc1 bc0 any other character --- b - fc2 fc1 fc0 bit symbol description 7 to 5, 3 - reserved. with osdt = new line; note 1 4 e end; if the e bit is 1, no further rows are displayed on the screen. 2 sr short row; if e = 0 and sr = 1, the next row is a short row, i.e. it is only 4 or 8 scan lines high rather than 18 or 36. short rows can be used for underlined text. 1 d double height; if e = 0 and d = 1, all of the characters in the following row are displayed with double height and width. 0 sh shadowing; if e = 0 and sh = 1, all of the characters in the following row are displayed with shadowing; see section 13.8. with osdt = bspace or splitbspace; note 2 4 b background; b indicates whether background pixels should show the current background colour (b = 1), or television video (b = 0). 2 to 0 bc2 to bc0 bcolor: background colour (notes 3 and 4; see table 22). with osdt = any other character 4 b background; b indicates whether background pixels should show the current background colour (b = 1), or television video (b = 0). 2 to 0 fc2 to fc0 fcolor: foreground colour. fcolor indicates the colour of foreground pixels in the rom bit map for this character (see table 22).
1996 mar 22 21 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 notes to the description of osat bits 1. the latches in which the e,sr, d, and sh bits are captured are cleared to zero at the start of each vertical scan. this means that if the first text line on the screen is a short row, or if it contains either double size or shadowing, the text must be preceded by a new line character. like all such characters, this initial new line advances the vertical screen position; the vstart value (see register osorg; section 13.9) should take this fact into account. 2. for splitbspace, a change in b and bcolor occurs halfway through the character horizontally. 3. the normal space character has no effect on the bcolor value. 4. the bcolor value is not cleared between vertical scans, so that if a single background colour is all that is needed in an application, it can be set via a single bspace character during program initialization, and never changed thereafter. in order for such a bspace to actually affect the 83c055 internal bcolor register the mode field of the osmod register must be set to 01b (or higher) so that the osd hardware is operating (see register osmod; section 13.8). table 22 osd outputs related to character bit map value, fcolor, bcolor and b bits notes 1. bcolor (bc2,bc1,bc0) values 000 and 111 minimize the occurrence of transient states among the vid2 to vid0 outputs. 2. the background colour defined by the most recently encountered bspace or splitbspace character is maintained on the vid2 to vid0 pins except at the following times: a) during the active time of hsync. b) during the active time of vsync. c) during those pixels of an active character that correspond to a logic 1 in the characters bit map. d) during a shadow bit. character bit map value osd outputs (notes 1 and 2) vid2 vid1 vid0 vctrl logic 1 fc2 fc1 fc0 driven active logic 0 bc2 bc1 bc0 b
1996 mar 22 22 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 13.7 osd control register oscon table 23 osd control register oscon (address c0h) table 24 description of oscon bits (see note 1) note 1. it is theoretically possible that a vsync interrupt could be missed, or an extra one generated, if oscon is read, then modified internally (e.g. in acc), and the result written back to oscon. however, none of the other bits in oscon are reasonable candidates for dynamic change. special provisions are included in the 83c055 logic so that iv will not be changed by a single read-modify-write instruction such as setb or clr, unless the instruction specifically changes iv. 76543210 iv pv lv ph pc po dh bfe bit symbol description 7 iv interrupt ?ag for the osd feature. bit iv is set by the leading edge of the vsync pulse, and is cleared by the hardware when the vsync interrupt routine is vectored to. it can also be set or cleared by software writing a logic 1 or logic 0 to this bit. 6 pv pv defines the active vsync input polarity. if pv = 0, then vsync input is active high; if pv = 1, then vsync input is active low. one effect of bit pv is that the vid2 to vid0 and vctrl outputs are blocked (held at black/inactive) during the active time of vsync. the iv bit is set on the leading edge of the vsync pulse; thus pv controls whether the osd interrupt occurs in response to a high-to-low or low-to-high transition on vsync. 5 lv lv de?nes the active edge of vsync. the active edge (leading or trailing) of vsync (as de?ned by pv), clears the state counter which determines the vertical start of on screen data. time reference for the video ?eld is the leading edge of vsync, if lv = 0, or the trailing edge of vsync, if lv = 1. 4 ph ph de?nes the active hsync input polarity. if ph = 0, then hsync input is active high; if ph = 1, then hsync input is active low. 3 pc pc de?nes the active vctrl output polarity; vctrl output active means: show the colour on vid2 to vid0. if pc = 0, then vctrl output is active high; if pc = 1, then vctrl output is active low. 2 po po defines the vid2 to vid0 outputs polarity; bit is needed only because the shadowing feature needs to generate black pixels without reference to a register value. internally, the 3-bit code 000b always designates black. if po = 0, a logic 0 internal to the 83c055 corresponds to a low on one of the vid2 to vid0 pins. if po = 1, a logic 1 internal to the 83c055 corresponds to a low on one of the vid2 to vid0 pins. 1 dh if dh = 1, character sizes are doubled vertically but not horizontally. this feature allows the 83c055 to be used in improved definition systems that are not interlaced. the vertical doubling imposed by dh does not affect the vstart logic as described in table 30; it operates in hsync units regardless of dh or d. 0 bfe background/foreground enable; output bf. if bfe = 1, then the bf output tracks whether each bit in displayed characters is a foreground bit (low), or a background bit (high). if bfe = 0, then the bf pin remains high.
1996 mar 22 23 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 13.8 osd control register osmod under some conditions writing to osmod while the display is active can cause a temporary flicker during that display field. this can be avoided by only writing to osmod during the vertical sync interval. table 25 osd control register osmod (address c1h) table 26 description of osmod bits (see note ) table 27 selection of display modes notes 1. a direct transition from this mode to active display (mode1, mode0 = 1x) would result in undefined operation and visual effects for the duration of the current video field (until the next vsync). 2. the osd feature can be toggled between this state and active display as desired to achieve real-time special effects such as vertical wiping. 3. since vid2 to vid0 are driven with the current background colour during this time, except during the foreground portion of displayed characters, this produces text against a solid background. this mode is useful for extensive displays that require user concentration. 76543210 wc - mode1 mode0 - shm2 shm1 shm0 bit symbol description 7 wc if wc = 1, then each displayed character is horizontally terminated after 12 bits have been output, as opposed to after 14 bits if wc = 0. this allows text to be packed more tightly so that more characters can be displayed per line. in effect, the 2 bits out of the display rom, which would otherwise be the rightmost 2 of the 14, are ignored when wc is 1. clearly, if this feature is to be used, it must be accounted for in the design of the bit maps in the display rom. 6 - reserved. 5 mode1 display mode select bits; see table 27. 4 mode0 3 - reserved. 2 to 0 shm2 to shm0 shadowing mode (shmode); determines how characters are shadowed in rows for which the row attribute sh = 1 (register osat; see table 21); for the shadowing modes see fig.8 and table 28. mode1 mode0 display mode 0 0 mode 0 the osd feature is disabled. vclk oscillator is disabled, vid2 to vid0 are set to black, and vctrl is held inactive.this is the mode to which the 83c055 osd logic is reset; note 1. 0 1 mode 1 the vclk oscillator is enabled and the osd logic operates normally internally, but vid2 to vid0 are set to black and vctrl is held inactive; note 2. 1 0 mode 2 normal osd operation. active characters can be shown against tv video (for characters with b = 0) or (for characters with b = 1) against a background of the colour defined as an attribute of bspace and splitbspace characters. 1 1 mode 3 characters can be displayed but all of the receivers normal video is inhibited by holding vctrl asserted throughout the active portion of each scan line; see note 3.
1996 mar 22 24 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 table 28 shadowing modes determined by bits shm2 to shm0 (register osmod) and sh (register osat) note 1. the mode names are based on the position of an apparent light source, ranging from the lower left (south-west) clockwise to the lower right (south-east); see fig.8. 13.9 osd control register osorg table 29 osd control register osorg (address c2h) table 30 description of osorg bits (note 1) notes 1. neither the hstart nor vstart parameter is affected by the d line attribute that is used to display double-sized characters. 2. counting variations in wc, there may be 17 to 143 vclk clock cycles from the end of hsync to the start of the first character of each row. 3. subsequent character rows occur directly below the first, such that the last scan line of one row is directly followed by the first scan line of the next row. successive new line characters (with or without the short row designation) can be used to vertically separate text rows on the screen. shm2 shm1 shm0 sh shadowing mode (1) 0 0 0 1 south-west 0 0 1 1 west 0 1 0 1 north-west 0 1 1 1 north 1 0 0 1 north-east 1 0 1 1 east 1 1 0 1 south-east 1 1 1 1 full surround x x x 0 no shadowing 76543210 hs4 hs3 hs2 hs1 hs0 vs2 vs1 vs0 bit symbol description 7 to 3 hs4 to hs0 hstart ?eld; de?nes the horizontal start position of all the on-screen character rows, as approximately a multiple of 4 vclk clock cycles. active display begins after the trailing edge of hsync at the position: where (hstart) is the decimal value of bits (hs4 to hs0); note 2. 2 to 0 vs2 to vs0 vstart ?eld; de?nes the vertical start position of the ?rst on-screen character row, as approximately a multiple of 4 hsync pulses. active display begins after the ?elds time reference point (a range of 3 to 31)at the position: where (vstart) is the decimal value of bits (vs2 to vs0); note 3. hp 4 hstart () 1 + [] vclk clock cycle one single-sized character width () + = vp 4 vstart () 1 C [] hsync pulses =
1996 mar 22 25 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 handbook, full pagewidth mbe773 shmode = 100 shmode = 011 shmode = 010 shmode = 101 no shadowing shmode = 001 shmode = 110 shmode = 111 shmode = 000 foreground colour pixel black pixel background colour pixel apparent light source fig.8 effect of shadowing on the letter e. shmode = (shm2, shm1, shm0)
1996 mar 22 26 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 14 programming considerations 14.1 eprom characteristics the 87c055 is programmed by using a modified quick-pulse programming algorithm similar to that used for devices such as the 87c751. it differs from these devices in that a serial data stream is used to place the 87c055 in the programming mode. figure 9 shows a block diagram of the programming configuration for the 87c055. table 31 pin usage for programming note 1. multiplexing of these address components is performed using the asel input: a) asel input is driven high and then drive port 2 with the high-order bits of the address. asel should remain high for at least 13 clock cycles. b) asel may then be driven low which latches the high-order bits of the address internally. the high-order address should remain on port 2 for at least 2 clock cycles after asel is driven low. c) port 2 may then be driven with the low byte of the address. the low-order address will be internally stable 13 clock cycles later. the address will remain stable provided that the low byte placed on port 2 is held stable and asel is kept low. d) asel needs to be pulsed high only to change the high byte of the address. pin usage xtal1 oscillator input and receives the master system clock. this clock should be between 1.2 and 6 mhz. reset used to accept the serial data stream that places the 87c055 into various programming modes. this pattern consists of a 10-bit code with the lsb sent first. each bit is synchronized to the clock input, xtal1. port 0 v pp /tdac/p0.0 used as the programming voltage supply input (v pp signal). prog/pwm1/p0.1 used as the program prog signal. this pin is used for the 25 programming pulses. port 2 p2.7 to p2.0 address input for the byte to be programmed and accepts both the high- and low-order components of the 11-bit address; note 1. port 3 p3.7 to p3.0 used as a bidirectional data bus during programming and verify operations. during programming mode, it accepts the byte to be programmed. during verify mode, it provides the contents of the eprom location specified by the address which has been supplied to port 2.
1996 mar 22 27 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 14.2 programming operation figures 10 and 11 show the timing diagrams for the program/verify cycle. programming operation: 1. rst should initially be held high for at least 2 machine cycles. p0.1 (prog) and p0.0 (v pp ) will be at v oh as a result of the rst operation. at this point, these pins function as normal quasi-bidirectional i/o ports and the programming equipment may pull these lines low. however, prior to sending the 10-bit code on the rst pin, the programming equipment should drive these pins high (v ih ). 2. the rst pin may now be used as the serial data input for the data stream which places the 87c055 in the programming mode. data bits are sampled during the clock high time and thus should only change during the time that the clock is low. following transmission of the last data bit, the rst pin should be held low. 3. next the address information for the location to be programmed is placed on port 2 and asel is used to perform the address multiplexing, as previously described (see table 31; note 1). a) at this time, port 1 functions as an output. b) a high voltage v pp level is then applied to the v pp input (p0.0). this sets port 1 as an input port. c) the data to be programmed into the eprom array is then placed on port 3. this is followed by a series of programming pulses applied to the prog pin (p0.1). these pulses are created by driving p0.1 low and then high. this pulse is repeated until a total of 25 programming pulses have occurred. at the conclusion of the last pulse, the prog signal should remain high. 4. the v pp signal may now be driven to the v oh level, placing the 87c055 in the verify mode; port 3 is now used as an output port. after four machine cycles (48 clock periods), the contents of the addressed location in the eprom array will appear on port 3. 5. the next programming cycle may now be initiated by: a) placing the address information at the inputs of the multiplexed buffers. b) driving the v pp pin to the v pp voltage level. c) providing the byte to be programmed to port 3 and issuing the 26 programming pulses on the prog pin. d) bringing v pp back down to the v oh level and verifying the byte (see table 33). 14.3 erasure characteristics erasure of the eprom begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4000 angstroms. since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadvertent erasure. for this and secondary effects, it is recommended that an opaque label be placed over the window. for elevated temperature or environments where solvents are being used, apply kapton tape fluorless (part number 2345-5) or equivalent. the recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrated dose of at least 15 ws/cm 2 . exposing the eprom to an ultraviolet lamp of 12000 m w/cm 2 rating for 20 to 39 minutes, at a distance of about 1 inch, should be sufficient. erasure leaves the array in an all logic 1s state. 14.4 reading signature bytes the signature bytes are read by the same procedure as a normal verify of locations 30h and 31h (the values are shown in table 32), except that the serial code indicated in table 33 for reading signature bytes should be used. table 32 programming and veri?cation codes table 33 implementing program/verify modes note 1. pulsed from v ih to v il and returned to v ih . address content indication 30h 15h manufactured by philips 31h 4bh 87c055 operation serial code p0.1 (prog) p0.0 (v pp ) program user eprom 286h - (1) v pp verify user eprom 286h v ih v ih read signature bytes 280h v ih v ih
1996 mar 22 28 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 fig.9 programming configuration. handbook, full pagewidth a0-a15 p2.0-2.7 v dd v ss p0.2/asel p0.1 p0.0 xtal1 p3.0-p3.7 reset address strobe programming pulses v pp /v ih voltage source clk source reset control logic 8 5v 8 data bus 87c055 mbe767 fig.10 entry into program/verify modes. handbook, full pagewidth bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 min 2 machine cycles 10-bit serial code undefined undefined xtal1 reset p0.0 p0.1 mbe768
1996 mar 22 29 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 14.5 eprom programming and veri?cation v dd =5v 10%; v ss =0v; t amb =21to27 c. note 1. address should be valid at least 24t clcl before the rising edge of p0.0 (v pp ). symbol parameter min. max. unit 1/t clcl oscillator/clock frequency 1.2 6 mhz t avgl (1) address setup to p0.1 (prog) low 10 + 24t clcl -m s t ghax address hold after p0.1 (prog) high 48t clcl -m s t dvgl data setup to p0.1 (prog) low 38t clcl -m s t ghdx data hold after p0.1 (prog) high 36t clcl -m s t shgl v pp setup to p0.1 (prog) low 10 -m s t ghsl v pp hold after p0.1 (prog) high 10 -m s t glgh p0.1 (prog) width 90 110 m s t avqv (1) v pp (v dd ) low to data valid - 48t clcl m s t ghgl p0.1 (prog) high to p0.1 (prog) low 10 -m s t synl p0.0 (sync pulse) low 4t clcl -m s t synh p0.0 (sync pulse) high 8t clcl -m s t masel asel high time 13t clcl -m s t hahld address hold time 2t clcl -m s t haset address setup to asel 13t clcl -m s t adsta low address to address stable 13t clcl -m s fig.11 program/verify cycle. h andbook, full pagewidth t masel t haset t hahld t avqv t ghdx t dvgl t adsta t glgh t ghgl t ghsl t shgl p0.0 [v (p-p)] p0.1 (prog) p0.2 (asel) port 2 port 3 5 v 12.75 v 5 v 98 m s min 10 m s min 25 pulses high address low address invalid data valid data valid data invalid data data to be programmed verify mode verify mode program mode mbe769
1996 mar 22 30 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 15 programming the osd eprom 15.1 overview the osd eprom space starts at location c000h and ends at location cfffh. however, due to the addressing scheme of the osd, not all locations within this space are used.the start location of the next character can be calculated by adding 40h to the start location of the previous character. for example, character 1 starts at c000h; then characters 2, 3, and 4 start at c040h, c080h, and c0c0h, respectively. 15.2 character description and programming an example of an osd character bit map, and the program data to obtain that character is shown in table 34. each character is 14 bits wide by 18 lines high.a character is split about a vertical axis into two sections upper and lower as illustrated in table 34: each section contains 7 bits of the character, such that: C the lower section contains bits 7 to 1, and C the upper section contains bits 14 to 8. the lower section of the character is programmed when the lsb of the program address equals a logic 0, and the upper section when the lsb equals a logic 1. during programming and verification, each section is programmed using bytes of program data. the msb of the program data is not used; however, the msb location physically exists, and so will program and verify. 15.3 osd eprom bit map the mapping for the full osd eprom is shown in table 35. to program the example character into the first character location of the osd eprom would require the data at the address as shown in table 34. table 34 example of an osd character bit map (note 1) note 1. x can be a logic 0 or logic 1, and will program and verify correctly. line character bit map program data address (hex) upper (bit 14 to 8) lower (bit 7 to 1) upper lower upper lower line 1 0000000 0000000 x0000000 x0000000 c001 c000 line 2 0000000 0000000 x0000000 x0000000 c003 c002 line 3 0011110 0001100 x0011110 x0001100 c005 c004 line 4 0011110 0001100 x0011110 x0001100 c007 c006 line 5 0011110 0001100 x0011110 x0001100 c009 c008 line 6 0011110 0001100 x0011110 x0001100 c00b c00a line 7 0011110 0001100 x0011110 x0001100 c00d c00c line 8 0011110 0001100 x0011110 x0001100 c00f c00e line 9 0011111 1111100 x0011111 x1111100 c011 c010 line 10 0011111 1111100 x0011111 x1111100 c013 c012 line 11 0011111 1111100 x0011111 x1111100 c015 c014 line 12 0011110 0001100 x0011110 x0001100 c017 c016 line 13 0011110 0001100 x0011110 x0001100 c019 c018 line 14 0011110 0001100 x0011110 x0001100 c01b c01a line 15 0011110 0001100 x0011110 x0001100 c01d c01c line 16 0011110 0001100 x0011110 x0001100 c01f c01e line 17 0000000 0000000 x0000000 x0000000 c021 c020 line 18 0000000 0000000 x0000000 x0000000 c023 c022
1996 mar 22 31 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 table 35 osd eprom bit map notes 1. characters 1 to 59 are setup in the similar way as character 0; due to space and simplicity this is not fully displayed. 2. locations 60, 61, 62 and 63 should be programmed to logic 0s. the character names are: character no. 60 = normal space; character no. 61 = new line; character no. 62 = bspace; character no. 63 = splitbspace. character no. address (hex) character line no. lower byte upper byte 0 c000 c001 1 c002 c003 2 c004 c005 3 c006 c007 4 c008 c009 5 c00a c00b 6 c00c c00d 7 c00e c00f 8 c010 c011 9 c012 c013 10 c014 c015 11 c016 c017 12 c018 c019 13 c01a c01b 14 c01c c01d 15 c01e c01f 16 c020 c021 17 c022 c023 18 c024 to c03f not used 1 (1) c040 to c063 1 to 18 c064 to c07f not used 2 (1) c080 to c0a3 1 to 18 c0a4 to c0bf not used 3to59 (1) -- 60 (2) cf00 to cf23 1 to 18 cf24 to cf3f not used 61 (2) cf40 to cf63 1 to 18 cf64 to cf7f not used 62 (2) cf80 to cfa3 1 to 18 cfa4 to cfbf not used 63 (2) cfc0 to cfe3 1 to 18 cfe4 to cfff not used
1996 mar 22 32 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 16 register map table 36 register map values within parenthesis show the bit state after a reset operation; x denotes an undefined state. addr. (hex) register 7 6 5 4 3210 e0 acc (1) acc7 (0) acc6 (0) acc5 (0) acc4 (0) acc3 (0) acc2 (0) acc1 (0) acc0 (0) f0 b (1) b7 (0) b6 (0) b5 (0) b4 (0) b3 (0) b2 (0) b1 (0) b0 (0) 83 dph dph7 (0) dph6 (0) dph5 (0) dph4 (0) dph3 (0) dph2 (0) dph1 (0) dph0 (0) 82 dpl dpl7 (0) dpl6 (0) dpl5 (0) dpl4 (0) dpl3 (0) dpl2 (0) dpl1 (0) dpl0 (0) a8 ie (1) ea (0) - (x) - (0) evs (0) et1 (0) ex1 (0) et0 (0) ex0 (0) 9a osad - (x) osad6 (x) osad5 (x) osad4 (x) osad3 (x) osad2 (x) osad1 (x) osad0 (x) 9f to 98 osat (1)(2) - (x) - (x) - (x) e (x) - (x) sr (x) d (x) sh (x) osat (1)(3) - (x) - (x) - (x) b (x) - (x) bc2 (x) bc1 (x) bc0 (x) osat (1)(4) - (x) - (x) - (x) b (x) - (x) fc2 (x) fc1 (x) fc0 (x) 99 osdt - (x) - (x) osdt5 (x) osdt4 (x) osdt3 (x) osdt2 (x) osdt1 (x) osdt0 (x) c0 oscon (1) iv (x) pv (x) lv (x) ph (x) pc (x) po (x) dh (x) bfe (x) c1 osmod wc (x) - (x) mode1 (x) mode0 (x) - (x) shm2 (x) shm1 (x) shm0 (x) c2 osorg hs4 (x) hs3 (x) hs2 (x) hs1 (x) hs0 (x) vs2 (x) vs1 (x) vs0 (x) 80 p0 (1) p07 (1) p06 (1) p05 (1) p04 (1) p03 (1) p02 (1) p01 (1) p00 (1) 90 p1 (1) p17 (1) p16 (1) p15 (1) p14 (1) p13 (1) p12 (1) p11 (1) p10 (1) a0 p2 (1) p27 (1) p26 (1) p25 (1) p24 (1) p23 (1) p22 (1) p21 (1) p20 (1) b0 p3 (1) p37 (1) p36 (1) p35 (1) p34 (1) p33 (1) p32 (1) p31 (1) p30 (1) 87 pcon - (0) - (x) - (x) - (x) gf1 (x) gf0 (x) - (x) - (x) d0 psw (1) cy (0) ac (0) f0 (0) rs1 (0) rs0 (0) ov (0) - (0) p (0) d4 pwm0 pw0e (0) - (0) pv05 (0) pv04 (0) pv03 (0) pv02 (0) pv01 (0) pv00 (0)
1996 mar 22 33 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 notes 1. bit addressable. 2. with osdt = new line. 3. with osdt = bspace or splitbspace. 4. with osdt = any other character. d5 pwm1 pw1e (0) - (0) pv15 (0) pv14 (0) pv13 (0) pv12 (0) pv11 (0) pv10 (0) d6 pwm2 pw2e (0) - (0) pv25 (0) pv24 (0) pv23 (0) pv22 (0) pv21 (0) pv20 (0) d7 pwm3 pw3e (0) - (0) pv35 (0) pv34 (0) pv33 (0) pv32 (0) pv31 (0) pv30 (0) dc pwm4 pw4e (0) - (0) pv45 (0) pv44 (0) pv43 (0) pv42 (0) pv41 (0) pv40 (0) dd pwm5 pw5e (0) - (0) pv55 (0) pv54 (0) pv53 (0) pv52 (0) pv51 (0) pv50 (0) de pwm6 pw6e (0) - (0) pv65 (0) pv64 (0) pv63 (0) pv62 (0) pv61 (0) pv60 (0) df pwm7 pw7e (0) - (0) pv75 (0) pv74 (0) pv73 (0) pv72 (0) pv71 (0) pv70 (0) d8 sad (1) vhi (0) ch1 (0) ch0 (0) st (0) sad3 (0) sad2 (0) sad1 (0) sad0 (0) 81 sp sp7 (0) sp6 (0) sp5 (0) sp4 (0) sp3 (0) sp2 (0) sp1 (0) sp0 (0) d3 tdach tde (0) - (0) td13 (0) td12 (0) td11 (0) td10 (0) td9 (0) td8 (0) d2 tdacl td7 (0) td0 (0) td1 (0) td2 (0) td3 (0) td4 (0) td5 (0) td6 (0) 8f tcon (1) tf1 (0) tr1 (0) tf0 (0) tr0 (0) ie1 (0) it1 (0) ie0 (0) it0 (0) 8c th0 th07 (0) th06 (0) th05 (0) th04 (0) th03 (0) th02 (0) th01 (0) th00 (0) 8d th1 th17 (0) th16 (0) th15 (0) th14 (0) th13 (0) th12 (0) th11 (0) th10 (0) 8a tl0 tl07 (0) tl06 (0) tl05 (0) tl04 (0) tl03 (0) tl02 (0) tl01 (0) tl00 (0) 8b tl1 tl17 (0) tl16 (0) tl15 (0) tl14 (0) tl13 (0) tl12 (0) tl11 (0) tl10 (0) 89 tmod gate (0) c/t (0) m1 (0) m0 (0) gate (0) c/t (0) m1 (0) m0 (0) c3 ramchr for test purposes only c4 ramatt for test purposes only addr. (hex) register 7 6 5 4 3210
1996 mar 22 34 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 17 limiting values in accordance with the absolute maximum rating system (iec 34); see notes 1 and 2. notes 1. stresses above those listed under limiting values may cause permanent damage to the device. 2. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. 18 handling inputs and outputs are protected against electrostatic discharge in normal handling. however it is good practice to take normal precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter min. max. unit v dd supply voltage 4.5 5.5 v v i input voltage on any pin with respect to ground (v ss ) - 0.5 6.5 v i oh maximum source current for all port lines -- 1.5 ma i ol maximum sink current for all port lines - 15 ma p tot total power dissipation - 1.5 w t amb operating ambient temperature 0 70 c t stg storage temperature - 65 150 c
1996 mar 22 35 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 19 dc characteristics v dd =5v 10% t amb = 0 to +70 c; all voltages with respect to v ss ; unless otherwise speci?ed. notes 1. i dd measured with osd block initialized and rst remaining low. 2. this maximum applies at all times, including during power switching, and must be accounted for in power supply design. during a power-on process, the +12 v source used for external pull-up resistors should not precede the v dd of the 83c055 up their respective voltage ramps by more than this margin, nor, during a power-down process, should v dd precede +12 v down their respective voltage ramps by more than this margin. 3. no more than 6 (any 6) of these 10 high current outputs may be used at the v ol1 (i ol = 10 ma) specification. the other 4 should comply with the v ol3 specification (i ol = 1.6 ma). 4. the specified current rating applies when any of these pins is used as a pulse width modulated (pwm) output. for use as a port output, the rating is as given subsequently. 5. the capacitance of pins p0.0 and p0.7 for the 87c055 exceeds 10 pf; for p0.0 this is maximum 40 pf, while for p0.7 it is maximum 20 pf. symbol parameter conditions min. typ. max. unit supply v dd operating supply voltage 4.5 5.0 5.5 v i dd operating supply current v dd = 5.5 v; note 1 -- 30 ma v il low level input voltage - 0.5 - 0.2v dd - 0.1 v v il1 low level input voltage; vsync and hsync - 0.5 - 0.15v dd v v ih high level input voltage; xtal, vclk1 and rst 0.7v dd - v dd + 0.5 v v ih1 high level input voltage; p1.2 to p1.0, p3.6 to p3.5 and p3.3 to p3.1 0.2v dd + 0.9 - v dd + 0.5 v v ih2 high level input voltage; p1.3, p3.7,p3.4 and p3.0 0.2v dd + 0.9 - 12.6 v v ih3 high level input voltage; vsync and hsync 0.67v dd - v dd + 0.5 v v ih - v dd high level input voltage with respect to v dd ; port 0, p1.3, p3.7, p3.4 and p3.0 note 2 0.7v dd - v dd + 0.5 v v ol1 low level output voltage; p2.7 to p2.0 and p3.6 to p3.5 i ol = 10 ma; note 3 -- 0.5 v v ol2 low level output voltage; tdac and pwm0 to pwm7 i ol = 700 m a; note 4 -- 0.5 v v ol3 low level output voltage; all other outputs i ol = 1.6 ma -- 0.45 v v oh high level output voltage; port 1, vid2 to vid0, vctrl and bf i oh = - 60 m a 2.4 -- v r rst reset (rst) pull-down resistor 50 - 300 k w c io pin capacitance; except p0.0 and p0.7 test freq. = 1 mhz; t amb =25 c; note 5 -- 10 pf hys hysteresis; vsync and hsync 0.8 -- v
1996 mar 22 36 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 20 ac characteristics v dd =5v 10%; t amb = 0 to +70 c; all voltages with respect to v ss ; unless otherwise speci?ed. notes 1. the 83c055 is tested at its maximum xtal frequency, but not at any other (lower) rate. 2. these parameters apply only when an external clock signal is used. 3. these parameters assume equal loading at c l = 100 pf, for all the referenced outputs. these parameters are specified but not tested. symbol parameter conditions min. typ. max. unit 1/t clcl xtal frequency note 1 6 - 12 mhz t chcx xtal1 clock high time note 2 20 -- ns t clcx xtal1 clock low time 20 -- ns t clch xtal1 clock rise time -- 20 ns t chcl xtal1 clock fall time 5 - 20 ns 1/t vclcl vclk frequency 5 - 8 mhz ? t vcoh - t vcol ? rise versus fall time skew on any one of vid2 to vid0, vctrl and bf note 3 -- 40 ns ? t vcoh1 - t vcoh2 ? rise time skew between any two of vid2 to vid0, vctrl and bf -- 30 ns ? t vcol1 - t vcol2 ? fall time skew between any two of vid2 to vid0, vctrl and bf -- 30 ns
1996 mar 22 37 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 21 package outlines unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot270-1 90-02-13 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 38.9 38.4 14.0 13.7 3.2 2.9 0.18 1.778 15.24 15.80 15.24 17.15 15.90 1.73 5.08 0.51 4.0 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 42 1 22 21 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip42: plastic shrink dual in-line package; 42 leads (600 mil) sot270-1
1996 mar 22 38 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 22 soldering 22.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these cases reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 22.2 soldering by dip or wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 22.3 repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. 23 definitions 24 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1996 mar 22 39 philips semiconductors product speci?cation microcontrollers for tv and video (mtv) 83c145; 83c845 83c055; 87c055 notes
philips semiconductors C a worldwide company argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. (02) 805 4455, fax. (02) 805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. (01) 60 101-1256, fax. (01) 60 101-1250 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. (172) 200 733, fax. (172) 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. (359) 2 689 211, fax. (359) 2 689 102 canada: philips semiconductors/components: tel. (800) 234-7381, fax. (708) 296-8556 chile: see south america china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. (852) 2319 7888, fax. (852) 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032) 88 2636, fax. (031) 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. (358) 0-615 800, fax. (358) 0-61580 920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. (01) 4099 6161, fax. (01) 4099 6427 germany: p.o. box 10 51 40, 20035 hamburg, tel. (040) 23 53 60, fax. (040) 23 53 63 00 greece: no. 15, 25th march street, gr 17778 tavros, tel. (01) 4894 339/4894 911, fax. (01) 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, bombay 400 018 tel. (022) 4938 541, fax. (022) 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. (01) 7640 000, fax. (01) 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. (03) 645 04 44, fax. (03) 648 10 07 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. (0039) 2 6752 2531, fax. (0039) 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. (03) 3740 5130, fax. (03) 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02) 709-1412, fax. (02) 709-1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03) 750 5214, fax. (03) 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. 9-5(800) 234-7831, fax. (708) 296-8556 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. (040) 2783749, fax. (040) 2788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09) 849-4160, fax. (09) 849-7811 norway: box 1, manglerud 0612, oslo, tel. (022) 74 8000, fax. (022) 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (63) 2 816 6380, fax. (63) 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. (022) 612 2831, fax. (022) 612 2327 portugal: see spain romania: see italy singapore: lorong 1, toa payoh, singapore 1231, tel. (65) 350 2000, fax. (65) 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. (011) 470-5911, fax. (011) 470-5494 south america: rua do rocio 220 - 5th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil, p.o. box 7383 (01064-970), tel. (011) 821-2333, fax. (011) 829-1849 spain: balmes 22, 08007 barcelona, tel. (03) 301 6312, fax. (03) 301 4107 sweden: kottbygatan 7, akalla. s-16485 stockholm, tel. (0) 8-632 2000, fax. (0) 8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01) 488 2211, fax. (01) 481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1, p.o. box 22978, taipei 100, tel. (886) 2 382 4443, fax. (886) 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. (66) 2 745-4090, fax. (66) 2 398-0793 turkey : talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0212) 279 2770, fax. (0212) 282 6707 ukraine: philips ukraine, 2a akademika koroleva str., office 165, 252148 kiev, tel. 380-44-4760297, fax. 380-44-4766991 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181) 730-5000, fax. (0181) 754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800) 234-7381, fax. (708) 296-8556 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. (381) 11 825 344, fax. (359) 211 635 777 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31-40-2724825 scds48 ? philips electronics n.v. 1996 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 457041/1100/01/pp40 date of release: 1996 mar 22 document order number: 9397 750 00752

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